From the pattern of branching of leaf veins to the variety of interconnected pathways that spread the coronavirus, nature thrives on networks – grids that connect the different components of complex systems. Networks underlie real-life problems such as determining the most efficient route for a trucking company to deliver life-saving drugs and calculating the fewest number of mutations needed to turn one chain of DNA into another.
Instead of relying on software to tackle these computation-intensive puzzles, researchers at the National Institute of Standards and Technology (NIST) took an unconventional approach. They created a design for an electronic hardware system that directly mimics the architecture of many types of networks.
The researchers demonstrated that their proposed hardware system, using a computational technique known as racing logic, can solve a variety of complex puzzles both quickly and with minimal energy expenditure. Race logic requires less power and resolves network problems faster than competitive general-purpose computers.
The scientists, who include NIST’s Advait Madhavan and the University of Maryland at College Park and NIST’s Matthew Daniels and Mark Stiles, describe their work in Volume 17, Issue 3, May 2021 of the ACM Journal on Emerging Technologies in Computer Systems.
A key feature of race logic is that it encodes information differently from a standard computer. Digital information is typically encoded and processed using computer bit values - a “1” if a logic instruction is true and a “0” if it is false. When a bit toggles its value, say from 0 to 1, it means that a particular logical operation has been performed in order to solve a mathematical problem.
In contrast, racing logic encodes and processes information by representing it as time signals – the point at which a particular group of computer bits goes from 0 to 1. A large number of bit flips is the main cause of the large number. power. consumption in standard computers. In this regard, racing logic offers an advantage because time-coded signals involve only a few carefully orchestrated bit flips to process the information, requiring much less power than signals coded as 0 or 1.
The computation is then carried out by delaying certain time signals with respect to others, determined by the physics of the system studied. For example, consider a group of truck drivers who start at point A and need to deliver drugs to point E as quickly as possible. Different possible routes pass through three intersections – call them B, C, and D. To determine the most efficient route, the race logic circuit evaluates each possible segment of the route, such as AB and AD. If AB takes longer to travel than AD, either because the path is longer or has more traffic, AB will be assigned a longer delay time. In the team design, the longer delay is implemented by adding additional resistance to the slower segment.
Race logic does involve a race, but in this competition all truck drivers initially drive in different directions. To determine which route to the final destination is the fastest, they run through all possible routes through the various intermediate delivery points. Into the new circuit, NIST researchers inserted a group of time-coded signals at the starting point, each acting as a different driver that accelerates through the team’s simulated hardware circuit.
Each time a pilot arrives at one of his intermediate destination points in the race, the model system sends out new pilots (new time signals) which deploy in different directions to the remaining destinations. If a driver arrives at a destination where another driver has already been, that driver gives up because their path is no longer competitive. The winner of the race – the first driver to reach the end of the circuit – indicates the solution to the particular puzzle that the material has been programmed to solve.
Madhavan began his pioneering work on racing logic circuits as a graduate student at the University of California, Santa Barbara in 2016. These early systems used specialized circuits and silicon chips that were designed to simulate specific networks, such as DNA manipulation, and therefore could solve only a limited number of network-related problems.
At NIST, Madhavan and his colleagues began working on more advanced racing logic circuits. Simulations by Madhavan, Daniels and Stiles have shown that their design, which has yet to be incorporated into a functional device, can handle a much larger class of networks, allowing racing logic to grapple with a greater variety of computer puzzles. These puzzles include finding the best alignment between two proteins or two chains of nucleotides – the molecules that make up the building blocks of DNA – and determining the shortest path between two destinations in a network.
“We showed how to use memory, which was not used in previous implementations of racing logic, to create a more general time computer,” Stiles said. “Integrating memory will allow us to address a wide class of problems with the next racing logic chip that we plan to manufacture,” he added.
Researchers have now started to build the material according to their design.